The Challenge:

Developing a test system to generate high frequency clock signals in order to initiate serial data collection from SCE, collecting this serial data, sending data commands and pulse commands to SCE.

The Solution:

Using the National Instruments FPGA board, M-Series DAQ boards and GPIB board along with LabVIEWTM 8.0 software, NI FPGA 8.0 software, NI RIO 2.0 software and NI DAQmx drivers, we were able to provide highly reliable, easy to use and powerful test system within 4 Months.

Introduction:

Our client, a leading R&D organization, specializes in developing satellite control electronics. The control electronics need to be tested very precisely before using in the Satellite. The control unit receives command signals serially form the ground station. In response to these signals, the control electronics shifts data serially to the ground station. The output of SCE also involves analog voltage and temperature signals.

Application:

The SSM control electronics (SCE) contains two parts to be tested.

In the encoder testing part, the test system is meant to generate a data collection clock pattern, the frequency of which is user selectable form 100 to 1000 Hz. The frequency of the clock is again user selectable, 500 KHz or 1MHz. This clock pattern should stay high for some multiple of clock period, and then generate 20 clock pulses of selected frequency. In response to 20 rising edges of clock, the encoder will shift 20 bit data serially for the test system to read. The test system has to read this serial data, convert it to parallel data, apply EU conversion factor, finally display and log it for post processing. The timing diagram of signals is shown below.

In addition to collecting data in response to the clock pattern, the test system has to collect data in response to an index pulse, which is generated by the encoder once in every revolution of the mechanism.

The package testing consist of

a). Temperature monitoring:
The SCE system contains 10 thermistors to monitor temperature. The test system has to measure temperature using these thermistors. The acquired data has to be logged for post analysis.

b). Analog Voltage monitoring:
The SCE system contains various transducers to measure certain parameters like motor current, friction, etc. The test system has to acquire these voltage signals from SCE.

c). 4 MHz base clock:
This is the clock signal which the SCE uses to derive clock signals for other operations. This clock must be running to run the electronics.

d). Pulse commands:
The SCE system needs a pulse of 64mSec. to turn on or off some part of electronics. The test system has to generate these 10 pulse commands on 10 digital output lines. These pulse commands should be issued in a particular order. Therefore some kind of interlocking is required here. Figure below shows pulse timing information.

e). Data Command:
The SCE system need 16 bit data serially to set some reference value (Set point). The test system has to provide this 16 bit reference data to the SCE system. To input this data to the SCE system, the test system has to generate an 8 KHz clock and strobe signal along with the data. The timings of these signals are shown below.

f). Level Commands:
The SCE system needs two level commands. The test system has to generate these signals. These commands sends high or low signal on two digital output lines.

g). 8 Bit monitoring:
The SCE system gives 8 bit data serially on 12 digital lines. 6 out of these 12 lines are containing the same information as remaining 6. In fact 6, 8 bit lines are coming form primary channels of the system, while remaining 6 are coming from the redundant channels. The test system has to read these data lines. To read data, the test system should generate a clock signal of 40 KHz and a mode signal. In response to these signals the SCE system will shift out 8 bit data serially. The timings of these signals are shown below.

Out of 12, 8 bit data lines, 2 lines are the status lines, one from the primary channel and other from the redundant channel. The status lines give status information about the system. The remaining 10 channels are grouped together to form a word channel, and then converted to decimal equivalent and finally to the desired unit by applying the EU factor. This data after EU conversion is to be displayed to the user and logged for post processing.

h). 16 Bit monitoring:
The SCE system gives 16 Bit position data serially. This data corresponds to the position of mechanism the values of which ranges form 0 to 360 degree. The test system has to read this 16 bit position data. To read this data from SCE, the test system has to generate a data taking clock, the frequency of which is user selectable in between 150 to 250Hz. In response to each rising edge of this clock, the SCE system sends a 500 KHz signal, strobe, and data. The timings of these signals are shown below.

The test system after reading 16 bits of data has to convert it to parallel 16 bit blocks. The decimal equivalent of this data has to be multiplied by the EU factor to convert into angle equivalent.

i). Power supply control and monitoring:
The SCE system is powered using a GPIB controlled power supply. This power supply has to be controlled and monitored. The load current drawn from the power supply has to be logged for post processing.

The system also involves lot of processing on the logged data, which includes.

System Design:

The timing requirements of this application are very much critical. These requirements cannot be met using high speed digital input output cards. To meet these requirements a custom hardware is required. That is why NI FPGA 7831R board is used for this application. To acquire temperature and analog voltage signals, 2 numbers of NI M-Series DAQ cards are used each with 16 analog input channels. The GPIB controlled power supply is controlled and monitored using the NI GPIB card.

To interface SCE system with the test system, in the digital monitoring part, line drivers (26LS31), line receivers (26LS32) and input/output buffers (CD4050) are used. To interface the thermistors and voltage signals some more circuitry is used.

In the test system 40 digital lines of FPGA card are used, 20 lines form the M-series card are used to measure temperature and voltage signals.

Software Implementation:

The software is developed using LabVIEW 8.0. To generate custom hardware using 7831R board, NI FPGA 8.0 and NI RIO 2.0 software are used. To acquire temperature and analog voltage signals, NI DAQmx driver is used. To control the power supply, the power supply drivers written in LabVIEW are used.

The maximum rate up to which data can be acquired from 10 temperature and 10 voltage channels is 10 KS/S per channel. The temperature and voltage channels can also be sampled at different rates. On-line FFT is applied on the data from voltage channels. The acquired data is logged. The FPGA programming is done using FPGA software module along with RIO drivers. Data from FPGA board is transferred to the host with the help of 3 available DMA channels on the FPGA board. This data has to be taken fast enough so that previously acquired data is not accumulating on the FPGA target. The power supply has to be controlled and monitored using GPIB commands.

This application involves actions happening at different rates, like analog acquisition, 8 Bit monitoring, 16 Bit monitoring, online FFT, logging. All these things should happen simultaneously in parallel. This is the situation (Parallel loop actions happening simultaneously) which is best handled by LabVIEW.

Conclusion:

We were able to design and develop a test system that enabled our client to efficiently test their UUTs. Faster implementation of test system was possible due to graphical programming in LabVIEW along with FPGA software module. Lot of time was saved in writing the FPGA code. Also implementation of logic was much easy using the NI FPGA software module. This was only because of LabVIEW, FPGA software and hardware, and NI high speed data acquisition boards and supporting drivers, that we were able to meet a challenging system testing requirement.